/*++
"This software program is available to you under a choice of one of two
licenses.  You may choose to be licensed under either the GNU General Public
License (GPL) Version 2, June 1991, available at
http://www.fsf.org/copyleft/gpl.html, or the Intel BSD + Patent License,
the text of which follows:

"Recipient" has requested a license and Intel Corporation ("Intel") is willing
to grant a license for the software entitled InfiniBand(tm) System Software
(the "Software") being provided by Intel Corporation.

The following definitions apply to this License:

"Licensed Patents" means patent claims licensable by Intel Corporation which
are necessarily infringed by the use or sale of the Software alone or when
combined with the operating system referred to below.

"Recipient" means the party to whom Intel delivers this Software.
"Licensee" means Recipient and those third parties that receive a license to
any operating system available under the GNU Public License version 2.0 or
later.

Copyright (c) 1996-2003 Intel Corporation. All rights reserved.

The license is provided to Recipient and Recipient's Licensees under the
following terms.

Redistribution and use in source and binary forms of the Software, with or
without modification, are permitted provided that the following conditions are
met:
Redistributions of source code of the Software may retain the above copyright
notice, this list of conditions and the following disclaimer.

Redistributions in binary form of the Software may reproduce the above
copyright notice, this list of conditions and the following disclaimer in the
documentation and/or other materials provided with the distribution.

Neither the name of Intel Corporation nor the names of its contributors shall
be used to endorse or promote products derived from this Software without
specific prior written permission.

Intel hereby grants Recipient and Licensees a non-exclusive, worldwide,
royalty-free patent license under Licensed Patents to make, use, sell, offer
to sell, import and otherwise transfer the Software, if any, in source code
and object code form. This license shall include changes to the Software that
are error corrections or other minor changes to the Software that do not add
functionality or features when the Software is incorporated in any version of
a operating system that has been distributed under the GNU General Public
License 2.0 or later.  This patent license shall apply to the combination of
the Software and any operating system licensed under the GNU Public License
version 2.0 or later if, at the time Intel provides the Software to Recipient,
such addition of the Software to the then publicly available versions of such
operating system available under the GNU Public License version 2.0 or later
(whether in gold, beta or alpha form) causes such combination to be covered by
the Licensed Patents. The patent license shall not apply to any other
combinations which include the Software. No hardware per se is licensed
hereunder.

THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
DISCLAIMED. IN NO EVENT SHALL INTEL OR ITS CONTRIBUTORS BE LIABLE FOR ANY
DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE."
--*/


/*
 * Abstract:
 *	Generic inline assembly implementation for atomic operations.
 *
 * Environment:
 * 	Linux Kernel Mode
 *
 * $Revision: 1.1 $
 */


#ifndef _CL_ATOMIC_ASM_H_
#define _CL_ATOMIC_ASM_H_


#include <asm/system.h>


/* The default atomic functions return the desired value. */
#define __cl_atomic_inc( ptr )			atomic_inc_return( (atomic_t*)ptr )
#define __cl_atomic_dec( ptr )			atomic_dec_return( (atomic_t*)ptr )
#define __cl_atomic_add( ptr, val )		atomic_add_return( val, (atomic_t*)ptr )
#define __cl_atomic_sub( ptr, val )		atomic_sub_return( val, (atomic_t*)ptr )


/* These definitions only appear for kernel on the PPC, so we add them
 * here for non kernel compilations
>  */
#ifndef __KERNEL__

#ifdef CONFIG_SMP
#define SMP_ISYNC       "\n\tisync"
#else
#define SMP_ISYNC
#endif

/* Erratum #77 on the 405 means we need a sync or dcbt before every stwcx.
 *  * The old ATOMIC_SYNC_FIX covered some but not all of this.
 *   */
#ifdef CONFIG_IBM405_ERR77
#define PPC405_ERR77(ra,rb)     "dcbt " #ra "," #rb ";"
#else
#define PPC405_ERR77(ra,rb)
#endif



static __inline__ int atomic_add_return(int a, atomic_t *v)
{
	int t;

	__asm__ __volatile__(
		"1:     lwarx   %0,0,%2         # atomic_add_return\n\
		add     %0,%1,%0\n"
		PPC405_ERR77(0,%2)
		"       stwcx.  %0,0,%2 \n\
		bne-    1b"
		SMP_ISYNC
		: "=&r" (t)
		: "r" (a), "r" (&v->counter)
		: "cc", "memory");

	return t;
}

static __inline__ int atomic_sub_return(int a, atomic_t *v)
{
	int t;

	__asm__ __volatile__(
		"1:     lwarx   %0,0,%2         # atomic_sub_return\n\
		subf    %0,%1,%0\n"
		PPC405_ERR77(0,%2)
		"       stwcx.  %0,0,%2 \n\
		bne-    1b"
		SMP_ISYNC
		: "=&r" (t)
		: "r" (a), "r" (&v->counter)
		: "cc", "memory");

	return t;
}

static __inline__ int atomic_inc_return(atomic_t *v)
{
	int t;

	__asm__ __volatile__(
		"1:     lwarx   %0,0,%1         # atomic_inc_return\n\
		addic   %0,%0,1\n"
		PPC405_ERR77(0,%1)
		"       stwcx.  %0,0,%1 \n\
		bne-    1b"
		SMP_ISYNC
		: "=&r" (t)
		: "r" (&v->counter)
		: "cc", "memory");

	return t;
}

static __inline__ int atomic_dec_return(atomic_t *v)
{
	int t;

	__asm__ __volatile__(
		"1:     lwarx   %0,0,%1         # atomic_dec_return\n\
		addic   %0,%0,-1\n"
		PPC405_ERR77(0,%1)
		"       stwcx.  %0,0,%1\n\
		bne-    1b"
		SMP_ISYNC
		: "=&r" (t)
		: "r" (&v->counter)
		: "cc", "memory");

	return t;
}



static __inline__ unsigned long
xchg_u32(volatile void *p, unsigned long val)
{
	unsigned long prev;

	__asm__ __volatile__ ("\n\
						  1:      lwarx   %0,0,%2 \n"
						  PPC405_ERR77(0,%2)
						  "       stwcx.  %3,0,%2 \n\
						  bne-    1b"
						  : "=&r" (prev), "=m" (*(volatile unsigned long *)p)
						  : "r" (p), "r" (val), "m" (*(volatile unsigned long *)p)
						  : "cc", "memory");

	return prev;
}


/*
 * This function doesn't exist, so you'll get a linker error
 * if something tries to do an invalid xchg().
 */
extern void __xchg_called_with_bad_pointer(void);


static inline unsigned long __xchg(unsigned long x, void * ptr, int size)
{
	CL_ASSERT(size == 4);

	switch (size)
	{
	case 4:
		return (unsigned long )xchg_u32(ptr, x);
#if 0   /* xchg_u64 doesn't exist on 32-bit PPC */
	case 8:
		return (unsigned long )xchg_u64(ptr, x);
#endif /* 0 */
	}

#if 0  /* the compiler does not take this trick, so I added
	* the assertion for the PPC in the beginning of the
	* function */
	__xchg_called_with_bad_pointer();
	return x;
#endif /* 0 */

	return 0; /* If you reached here, then something
			  * really went wrong */
}

static __inline__ unsigned long

__cmpxchg_u32(volatile int *p, int old, int new)
{
	int prev;

	__asm__ __volatile__ ("\n\
						  1:      lwarx   %0,0,%2 \n\
						  cmpw    0,%0,%3 \n\
						  bne     2f \n"
						  PPC405_ERR77(0,%2)
						  "       stwcx.  %4,0,%2 \n\
						  bne-    1b\n"
#ifdef CONFIG_SMP
						  "       sync\n"
#endif /* CONFIG_SMP */
						  "2:"
						  : "=&r" (prev), "=m" (*p)
						  : "r" (p), "r" (old), "r" (new), "m" (*p)
						  : "cc", "memory");

	return prev;
}



/* This function doesn't exist, so you'll get a linker error
   if something tries to do an invalid cmpxchg().  */
extern void __cmpxchg_called_with_bad_pointer(void);

static __inline__ unsigned long
__cmpxchg(volatile void *ptr, unsigned long old, unsigned long new, int size)
{
	switch (size)
	{
	case 4:
		return __cmpxchg_u32(ptr, old, new);
#if 0   /* we don't have __cmpxchg_u64 on 32-bit PPC */
	case 8:
		return __cmpxchg_u64(ptr, old, new);
#endif /* 0 */
	}
	__cmpxchg_called_with_bad_pointer();
	return old;
}

#define cmpxchg(ptr,o,n)                                                 \
  ({                                                                     \
     __typeof__(*(ptr)) _o_ = (o);                                       \
     __typeof__(*(ptr)) _n_ = (n);                                       \
     (__typeof__(*(ptr))) __cmpxchg((ptr), (unsigned long)_o_,           \
                                    (unsigned long)_n_, sizeof(*(ptr))); \
  })


#endif /* ! defined __KERNEL__ */


#endif /* _CL_ATOMIC_ASM_H_ */
