****library: "sclib"
version: 6.05bi
aids: 14
aidname: user
aidname: io
aidname: compaction
aidname: pla
aidname: routing
aidname: silicon-compiler
variables: 4
SC_horiz_arc[015,00/00]: mocmos:Metal-1
SC_nwell_size[01,00/00]: 20400
SC_pwell_size[01,00/00]: 16400
SC_vert_arc[015,00/00]: mocmos:Metal-2
aidname: vhdl-compiler
aidname: compensation
aidname: logeffort
aidname: network
aidname: drc
aidname: erc
aidname: simulation
aidname: project
userbits: 6
techcount: 16
techname: generic lambda: 2000
techname: nmos lambda: 4000
techname: cmos lambda: 4000
techname: mocmos lambda: 400
variables: 1
TECH_last_state[01,00/00]: 8
techname: mocmosold lambda: 2000
techname: mocmossub lambda: 400
variables: 1
TECH_last_state[01,00/00]: 8
techname: bicmos lambda: 2000
techname: rcmos lambda: 2000
techname: cmosdodn lambda: 2000
techname: bipolar lambda: 4000
techname: schematic lambda: 4000
techname: fpga lambda: 2000
techname: pcb lambda: 2540000
techname: artwork lambda: 2000
variables: 1
TECH_last_state[01,00/00]: 0
techname: gem lambda: 2000
techname: efido lambda: 20000
view: schematic-page-2{p2}
view: schematic-page-1{p1}
view: layout{lay}
view: schematic{sch}
view: icon{ic}
view: documentation{doc}
view: compensated{comp}
view: skeleton{sk}
view: Verilog{ver}
view: VHDL{vhdl}
view: netlist{net}
view: netlist-als-format{net-als}
view: netlist-quisc-format{net-quisc}
view: netlist-silos-format{net-silos}
view: netlist-rsim-format{net-rsim}
view: netlist-netlisp-format{net-netlisp}
view: simulation-snapshot{sim}
view: unknown{}
cellcount: 15
maincell: 3
variables: 1
LIB_save_options[01,00/04]: 32768
***cell: 0
name: and3{lay}
version: 2
creationdate: 902609292
revisiondate: 979321191
lowx: -28000 highx: 18800 lowy: 400 highy: 50400
aadirty: 6638
userbits: 4194304
nodes: 58 arcs: 59 porttypes: 7
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rotation: 0 transpose: 0
userbits: 3080
*port: metal-1
arc: 0
arc: 1
exported: 6
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type: mocmos:Metal-1-P-Active-Con
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rotation: 0 transpose: 0
userbits: 3072
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arc: 2
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type: mocmos:Metal-1-Pin
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rotation: 0 transpose: 0
userbits: 1032
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arc: 4
arc: 5
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type: mocmos:Metal-1-P-Active-Con
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rotation: 0 transpose: 0
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type: mocmos:Metal-1-Pin
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rotation: 0 transpose: 0
userbits: 8
*port: metal-1
arc: 7
arc: 8
arc: 9
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rotation: 0 transpose: 0
userbits: 2048
*port: metal-1-metal-2
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exported: 5
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type: mocmos:Metal-1-Pin
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rotation: 0 transpose: 0
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arc: 11
arc: 12
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rotation: 0 transpose: 0
userbits: 2048
*port: metal-1-metal-2
arc: 10
exported: 4
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type: mocmos:Polysilicon-1-Pin
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rotation: 0 transpose: 0
userbits: 8
*port: polysilicon-1
arc: 13
arc: 14
arc: 15
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*port: metal-1
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arc: 22
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rotation: 0 transpose: 0
userbits: 3072
*port: metal-1-metal-2
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type: mocmos:Metal-1-Metal-2-Con
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rotation: 0 transpose: 0
userbits: 3072
*port: metal-1-metal-2
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type: mocmos:Metal-1-Metal-2-Con
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rotation: 0 transpose: 0
userbits: 3072
*port: metal-1-metal-2
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type: mocmos:Metal-1-Pin
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rotation: 0 transpose: 0
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*port: metal-1
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arc: 23
arc: 24
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*port: n-trans-diff-bot
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*port: n-trans-diff-top
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*port: n-trans-diff-bot
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*port: n-trans-diff-bot
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**node: 25
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rotation: 0 transpose: 0
userbits: 3072
*port: metal-1-n-act
arc: 0
arc: 32
**node: 26
type: mocmos:Metal-1-N-Active-Con
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rotation: 900 transpose: 0
userbits: 3072
*port: metal-1-n-act
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arc: 28
**node: 27
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rotation: 900 transpose: 0
userbits: 3072
*port: metal-1-n-act
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arc: 29
**node: 28
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userbits: 1032
*port: polysilicon-1
arc: 25
arc: 33
**node: 29
type: mocmos:Polysilicon-1-Pin
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rotation: 0 transpose: 0
userbits: 8
*port: polysilicon-1
arc: 25
arc: 35
arc: 37
**node: 30
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rotation: 0 transpose: 0
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*port: polysilicon-1
arc: 20
arc: 26
arc: 36
arc: 38
**node: 31
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arc: 39
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*port: metal-1
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arc: 9
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type: mocmos:Polysilicon-1-Pin
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rotation: 0 transpose: 0
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*port: polysilicon-1
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arc: 40
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subport: metal-1-p-act
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subport: metal-1-metal-2
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